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Masoumi, M., Dehghan, A., Madadi, E. (2020). Design and Production of Hardware Authentication Code Using Physically Unclonable Functions and a Random Number Generator on FPGA. Electronic and Cyber Defense, 7(4), 37-50.
M. Masoumi; A. Dehghan; E. Madadi. "Design and Production of Hardware Authentication Code Using Physically Unclonable Functions and a Random Number Generator on FPGA". Electronic and Cyber Defense, 7, 4, 2020, 37-50.
Masoumi, M., Dehghan, A., Madadi, E. (2020). 'Design and Production of Hardware Authentication Code Using Physically Unclonable Functions and a Random Number Generator on FPGA', Electronic and Cyber Defense, 7(4), pp. 37-50.
Masoumi, M., Dehghan, A., Madadi, E. Design and Production of Hardware Authentication Code Using Physically Unclonable Functions and a Random Number Generator on FPGA. Electronic and Cyber Defense, 2020; 7(4): 37-50.

Design and Production of Hardware Authentication Code Using Physically Unclonable Functions and a Random Number Generator on FPGA

پدافند الکترونیکی و سایبری
Article 4, Volume 7, Issue 4 - Serial Number 28, March 2020, Pages 37-50    PDF (1.2 M)
Document Type: Original Article
Authors
M. Masoumi* 1; A. Dehghan2; E. Madadi3
1عضو هیات علمی
2کارشناس ارشد
3-
Receive Date: 01 February 2019,  Revise Date: 26 April 2019,  Accept Date: 18 June 2019 
Abstract
 One of the most challenging issues in the field of hardware security is to protect the hardware from reverse engineering, counterfeiting and cloning. Using Physically Unclonable Functions (PUFs) is among the most efficient ways to improve security against these kinds of threats. In this work, we used a multiplexer-based or the so-called arbiter PUF to improve resilience of FPGAs from Xilinx family against these types of vulnerabilities. At first, a 32-bit random code was generated as the initial seed for a linear feedback shift register (LFSR). Then, a 64-bit unique authentication code was generated by XORing the outputs of the shift register and outputs of a ring oscillator-based random number generator and passing out the result from the Von Neumann corrector. The scheme is implemented in such a way that the generated code is robust against reverse engineering or modeling, and therefore is unrecoverable. The implementation results, on Side-Channel Attack User Reference Architecture (SAKURA G-II) which includes XC6SLX75 demonstrated that the design utilizes almost 15% of FPGA resources to generate a 64-bit unique authentication code.
Keywords
Hardware Security; Physically Unclonable Function; Random Number Generator; FPGA Implementation
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