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Rahimi Rizi, O., Mir, S., Mir-Moghtadaei, S. (2022). A High sensitive Envelope Detector with Very Low Transition Time Using 180 nm CMOS Technology for RADAR Applications. Electronic and Cyber Defense, 9(2), 15-23.
Omid Rahimi Rizi; seyyed Amir Hosein Mir; Sayed Vahid Mir-Moghtadaei. "A High sensitive Envelope Detector with Very Low Transition Time Using 180 nm CMOS Technology for RADAR Applications". Electronic and Cyber Defense, 9, 2, 2022, 15-23.
Rahimi Rizi, O., Mir, S., Mir-Moghtadaei, S. (2022). 'A High sensitive Envelope Detector with Very Low Transition Time Using 180 nm CMOS Technology for RADAR Applications', Electronic and Cyber Defense, 9(2), pp. 15-23.
Rahimi Rizi, O., Mir, S., Mir-Moghtadaei, S. A High sensitive Envelope Detector with Very Low Transition Time Using 180 nm CMOS Technology for RADAR Applications. Electronic and Cyber Defense, 2022; 9(2): 15-23.

A High sensitive Envelope Detector with Very Low Transition Time Using 180 nm CMOS Technology for RADAR Applications

رادار
Volume 9, Issue 2 - Serial Number 26, November 2022, Pages 15-23    PDF (1021.27 K)
Document Type: Original Article
Authors
Omid Rahimi Rizi1; seyyed Amir Hosein Mir1; Sayed Vahid Mir-Moghtadaei* 2
1Master's student, Shahrekord University, Shahrekord, Iran
2Assistant Professor, Shahrekord University, Shahrekord, Iran
Receive Date: 04 March 2021,  Revise Date: 20 November 2021,  Accept Date: 01 October 2022 
Abstract
This paper presents a high-sensitive envelope detector in 2.7GHz to 3.9GHz frequency band using 180 nm CMOS technology. The detector is based on the Successive Detection Logarithmic Amplifiers (SDLA) and consists of three sections: the detector core (rectifier), semi-logarithmic RF amplifier, and output stage. The detector core is based on the unbalanced source coupled method, which provides a full-wave rectifier. The frequency bandwidth and transition time of detector core are 0.1GHz to 10 GHz and 1ns, respectively. In this paper, the sensitivity of the detector is also improved about 2 dB by injecting part of the input signal into the tail current path. To amplify the signal, a proposed low-noise amplifier(LNA) with a single input and differential output and a simple differential amplifier in series are used. The output stage provides a low pass filter and drives a 2pF output capacitance, without increasing the transition time. By using RF power limiters in the outputs of LNA and differential amplifier, a semi-logarithmic behavior for the total circuit is obtained while preventing saturation of amplifiers due to the large input signal. Post-layout simulation results by Spectre-RF show the sensitivity of -45dBm and the rise and fall times of less than 1.2ns, which is a significant improvement compared to recent reported work. The semi-logarithmic dynamic range and the power consumption of this detector are 20dB and 12mW from a voltage source of 1.8V, respectively. The occupied area of the detector core is only 72µm×72µm, while the active area of the total detector, including amplifiers, limiters, rectifiers and output buffer is 0.7mm×0.55mm.
Keywords
Successive Envelope detector; Source Coupled; Semi-Logarithmic Amplifier; Limiter
References

[1]     Lakshminarayanan, S. & K. Hofmann, "A wideband RF power detector with− 56 dB sensitivity and 64 dB dynamic range in SiGe BiCMOS technology," in 2017 IEEE International Symposium on Circuits and Systems (ISCAS). 2017.

[2]     Holdenried, C.D., "A DC-4-GHz true logarithmic amplifier: theory and implementation," IEEE Journal of Solid-State Circuits, 37(10), pp. 1290-1299, 2002.

[3]     Kim, K. & Y. Kwon, "A Broadband Logarithmic Power Detector in 0.13-$\mu $ m CMOS," IEEE microwave and wireless components letters, 23(9), pp. 498-500, 2013.

[4]     Wu, J.-W., "A linear-in-dB radio-frequency power detector. in 2011 IEEE MTT-S International Microwave Symposium, 2011.

[5]     Shieh, M.-L., "Linear radio frequency power detector," in 2009 Asia Pacific Microwave Conference, 2009.

[6]     Chou, C.-C., "A low minimum detectable power, high dynamic range, V-band CMOS millimeter-wave logarithmic power detector," in 2017 IEEE MTT-S International Microwave Symposium (IMS), 2017.

[7]     Zhou, Y. & M.Y.-W. Chia, "A low-power ultra-wideband CMOS true RMS power detector. IEEE Transactions on Microwave Theory and Techniques," 56(5), pp. 1052-1058, 2008.

[8]     Kiela, K., M. Jurgo, & R. Navickas, "Design of a linear-in-dB power detector in 65nm CMOS technology," Elektronika ir Elektrotechnika, 19(10), pp. 91-94, 2013.

[9]     Wu, J.-W., "Closed-loop power control of radio frequency power amplifier module with an on-chip embedded power detector," in 2006 Asia-Pacific Microwave Conference, 2006.

[10]   Gertel, E., D.M. Johnson, & M. Kumar, "2-18 GHz logarithmic amplification componentry," in IEEE International Digest on Microwave Symposium, 1990.

[11]   Zhou, Y. & M.C.Y. Wah, "A wide band CMOS RF power detector," in 2006 IEEE International Symposium on Circuits and Systems, 2006.

[12]   Yong, Z., "A parallel-amplification parallel-summation logarithmic amplifier for UHF RFID reader," in 2009 IEEE 8th International Conference on ASIC, 2009.

[13]   Chadwick, P.E, "Advances in logarithmic amplifiers," in 1989 Fifth International Conference on Radio Receivers and Associated Systems, 1990.

[14]   Di Alessandro, L., "Robust GaN Successive-Detection Logarithmic Video-Amplifier for EW applications," in 2015 Integrated Nonlinear Microwave and Millimetre-wave Circuits Workshop (INMMiC), 2015.

[15]   Park, H., "A CMOS RF power detector using an improved unbalanced source coupled pair," IEICE transactions on electronics, 91(12), pp. 1969-1970, 2008.

[16]   Xia, J. & S. Boumaiza, "A novel broadband linear-in-magnitude RF envelope detector with enhanced detection speed and accuracy," IEEE Microwave and Wireless Components Letters, 25(5), pp. 325-327, 2015.

[17]   Cha, J., "A highly-linear radio-frequency envelope detector for multi-standard operation," in 2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009.

[18]   Zhou, Y., "A novel wide-band envelope detector," in 2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008.

[19]   Su, Y.-b., "A Highly Linear Low Power Envelope Detector," in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019.

[20]   Im, D., "A CMOS active feedback wideband single-to-differential LNA using inductive shunt-peaking for saw-less SDR receivers," in 2010 IEEE Asian Solid-State Circuits Conference, 2010.

[21]   Kimura, K, "A unified analysis of four-quadrant analog multipliers consisting of emitter and source-coupled transistors operable on low supply voltage," IEICE Transactions on Electronics, 76(5), pp. 714-737, 1993.

[22]   Kimura, K, "A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs," IEEE Journal of Solid-State Circuits, 28(1), pp. 78-83, 1993.

[23]   Nosratinia, A., "High-drive CMOS buffer for large capacitive loads," Electronics letters, 27(12), pp. 1044-1046, 1991.

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