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طراحی و تحقق یک مدار مقایسه‌کننده فرکانس مبتنی بر توابع فیزیکی غیرقابل کپی برداری برای محافظت از اصالت سختافزار | ||
| پدافند الکترونیکی و سایبری | ||
| مقاله 3، دوره 6، شماره 4 - شماره پیاپی 24، اسفند 1397، صفحه 23-32 اصل مقاله (1.51 M) | ||
| نوع مقاله: مقاله پژوهشی | ||
| نویسندگان | ||
| اقبال مددی1؛ مسعود معصومی* 2؛ علی دهقان منشادی1؛ ابوالفضل چمن مطلق3 | ||
| 1دانشگاه امام حسین (ع) | ||
| 2استادیار دانشگاه آزاد اسلامی واحد اسلامشهر | ||
| 3دانشگاه جامع امام حسین(ع) | ||
| تاریخ دریافت: 06 مهر 1396، تاریخ پذیرش: 06 خرداد 1397 | ||
| چکیده | ||
| یکی از چالشهای مهم در امنیت سختافزار مقابله با کپیسازی و استفاده از سختافزارهای جعلی بهجای سختافزارهای اصلی و واقعی است. در حقیقت هدف این نوع حمله خدشهدار کردن اصالت سختافزار است و هدف آن کشف کلید یا پارامترهای حساس ابزار رمز نیست. از اینرو، برای مقابله با آن باید تمهیدات ویژه و متفاوت با روشهای متداول محافظت از امنیت الگوریتمها و سامانهها در نظر گرفته شود. یکی از موثرترین روشهای مقابله با این نوع حملات و محافظت از اصالت سختافزار استفاده از توابع کپیناپذیر فیزیکی یا پاف است. توابع کپیناپذیر فیزیکی را میتوان برای استخراج پارامترهای مخفی از خصوصیات فیزیکی و ذاتی مدارهای مجتمع مورد استفاده قرار داد. فرآیندهای وابسته پافها میتوانند انواع و اقسام داشته باشند اما پافهای سیلیکونی که بر مبنای تاخیرها و زمانبندیهای خاص هر فرآیند هستند متداولتر هستند. در این مقاله تحقق عملی یک پاف سیلیکونی مبتنی بر نوسانساز حلقوی بر روی تراشههای FPGA از خانواده Xilinx گزارش شده است. نتایج پیادهسازی نشان داد که با استفاده از پنج نوسانساز حلقوی قادر به ارائه یک کد امنیتی منحصر بهفرد 10 بیتی با مصرف تقریبآ یک درصد از سطح تراشه هدف هستیم ضمن آنکه با صرف سختافزار بیشتر قادر به دستیابی به کدهای طولانیتر و امنیت بیشتر هستیم. تمامی شبیهسازیهای انجام شده بر روی یک رایانه قابل حمل با مشخصات پردازنده مرکزی از نوع دو هستهای با فرکانسGHz 2 و GB 4 حافظه RAM پیادهسازی شدهاند. | ||
| کلیدواژه‌ها | ||
| امنیت سختافزار؛ توابع کپیناپذیر فیزیکی؛ پیادهسازی FPGA | ||
| عنوان مقاله [English] | ||
| Design and Implementation of a Physically Unclonable Function on FPGA | ||
| نویسندگان [English] | ||
| Eqbal Madadi1؛ Masoud Masoumi2؛ Ali Dehqan Menshadi1؛ Abolfazl Chaman Motlaq3 | ||
| 2عضو هیات علمی | ||
| چکیده [English] | ||
| One of the challenges in the hardware security is withstanding cloning and hardware duplication. In fact this attack aims hardware originality so the defense mechanism should be different from common system security and algorithm protection. Applying Physically Unclonable Functions (PUFs) is one of the most effective protection methods. Physically Unclonable Functions (PUFs) are functions that generate a set of random responses when stimulated by a set of pre-defined requests or challenges. Since these challenge-response schemes extract hidden parameters of complex physical unpredictable properties of substrate materials, such as delay of interconnections and wiring in the CMOS process and devices, they are called physically unclonable functions. They are mainly used for electronic security purposes such as hardware verification and/or device authentication mechanisms, protection of sensitive intellectual property (IP) on devices and protection against insecure hardware connections and communications. PUF-based security mechanisms have some obvious advantages compared to traditional cryptography-based techniques, including more resistance against physical and side channel attacks and suitability for lightweight devices such as RFIDs. In FPGA devices, PUFs are instantiated by exploiting the propagation delay differences of signals caused by manufacturing process variations. However, real implementation of PUFs on FPGAs is a big challenge given the fact that the resources inside FPGAs are limited, and that it is not easy to simulate the behavior of PUF using existing software tools. In addition, there are a few articles that explain details of the implementation of PUFs on FPGAs. In practice, it usually takes a long time to get a simple PUF to work both in simulations and on board. In this work, we describe a practical realization of a ring-oscillator based PUF on Xilinx FPGAs and illustrate how such architecture is mapped into some FPGAs from this device family. Using this architecture, we obtain a unique 10-bit code which can be used to identify a chip between many similar devices of the same family in order to provide a reliable access control and authentication mechanism. Simulations are carried out using a dual core computer with 2 GHz clock frequency and 4 GBytes RAM memory. | ||
| کلیدواژه‌ها [English] | ||
| Hardware Security, Physically Unclonable Function, FPGA Implementation | ||
| مراجع | ||
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