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ارائه روشی جهت افزایش اتکاپذیری حافظهی نهان | ||
| پدافند الکترونیکی و سایبری | ||
| مقاله 1، دوره 10، شماره 1 - شماره پیاپی 37، خرداد 1401، صفحه 1-10 اصل مقاله (996.34 K) | ||
| نوع مقاله: مقاله پژوهشی | ||
| نویسندگان | ||
| مهدیه قزوینی* 1؛ محمدجواد شهنوازی2؛ بهنام قوامی1 | ||
| 1دانشیار، دانشگاه شهید باهنر کرمان، کرمان، ایران | ||
| 2کارشناسی ارشد، دانشگاه شهید باهنر کرمان، کرمان، ایران | ||
| تاریخ دریافت: 11 بهمن 1399، تاریخ بازنگری: 10 مرداد 1400، تاریخ پذیرش: 20 آذر 1400 | ||
| چکیده | ||
| پردازنده‌های مدرن که شامل حافظهی نهان بزرگ است، نسبت به خطاهای گذرا آسیب‌پذیری بالایی دارد. اهمیت این موضوع باعث شده است تا از روش‌های کدگذاری برای محافظت در برابر خطا استفاده شود. هزینه‌ی قابلیت اطمینان باید به نحوی تأمین گردد تا استفاده‌ی بهینه از انرژی و ناحیه را در پی داشته باشد. در این مقاله روشی برای افزایش اتکاپذیری حافظهی نهان محافظت نشده در پردازنده‌ها ارائه شده است. در این مقاله قابلیت اطمینان حافظهی نهان در پردازنده‌های مدرن با استفاده از مکانیسم کاهش خطای برچسب کم‌هزینه مورد مطالعه قرار می‌گیرد. روش پیشنهادی از تکنیک افزایش فاصله‌ی همینگ در برچسب بهره‌برداری می‌کند. علاوه‌بر کاهش False Hit به صفر ، دارای سربار بسیار پایین نیز هست. | ||
| کلیدواژه‌ها | ||
| فاصله‌ی همینگ؛ اتکاپذیری؛ False Hit؛ حافظهی نهان؛ اشکال | ||
| عنوان مقاله [English] | ||
| An Approach to Dependability Enhancement of Cache Memories | ||
| نویسندگان [English] | ||
| Mahdieh Ghazvini1؛ mohammadjavad shahnavazi2؛ Behnam Ghavami1 | ||
| 1Associate Professor, Shahid Bahonar University of Kerman, Kerman, Iran | ||
| 2Master's degree, Shahid Bahonar University of Kerman, Kerman, Iran | ||
| چکیده [English] | ||
| The modern processors that consist of large caches are very vulnerable to transient errors. Due to the importance of this problem, coding methods are adopted for protection against errors. The cost of reliability should be incurred to optimize the use of energy and area. This paper proposes an approach to dependability enhancement in unprotected caches of processors. For this purpose, the low-cost tag error mitigation mechanism is adopted to analyze the reliability of caches in modern processors. Benefiting from the tag Hamming distance increase technique, the proposed approach has a much lower overhead and decreases the false hit rate to zero. | ||
| کلیدواژه‌ها [English] | ||
| Hamming distance, reliability, false hit, cache memory, error | ||
| مراجع | ||
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[17] M. Kharbutli, Y. Solihin and Jaejin Lee, "Eliminating conflict misses using prime number-based cache indexing," in IEEE Transactions on Computers, vol. 54, no. 5, pp. 573-586, May 2005. [18] R. Ubal, B. Jang, P. Mistry, D. Schaa and D. Kaeli, "Multi2Sim: A simulation framework for CPU-GPU computing," 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, 2012, pp. 335-344. [19] Y. Arafa, A. A. Badawy, G. Chennupati, N. Santhi and S. Eidenbenz, "PPT-GPU: Scalable GPU Performance Modeling," in IEEE Computer Architecture Letters, vol. 18, no. 1, pp. 55-58, 1 Jan.-June 2019, doi: 10.1109/LCA.2019.2904497. [20] https://github.com/Multi2Sim/ [21] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen and N. P. Jouppi, "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures," 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, pp. 469-480 [22] C. W. Slayman, "Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations," in IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 397-404, Sept. 2005, doi: 10.1109/TDMR.2005.856487. | ||
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آمار تعداد مشاهده مقاله: 710 تعداد دریافت فایل اصل مقاله: 273 |
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