| تعداد نشریات | 34 |
| تعداد شماره‌ها | 1,290 |
| تعداد مقالات | 9,312 |
| تعداد مشاهده مقاله | 8,809,125 |
| تعداد دریافت فایل اصل مقاله | 5,346,625 |
ارائه روشی بهینه در سنتزکننده فرکانسی کسری -N برای کاهش توان مصرفی حلقه قفل فاز با مدولاتور دلتا سیگما در رادارهای باند X | ||
| رادار | ||
| مقاله 1، دوره 11، شماره 1، شهریور 1402، صفحه 1-14 اصل مقاله (1.03 M) | ||
| نوع مقاله: مقاله پژوهشی | ||
| نویسندگان | ||
| هومن اکبرزاده1؛ سعید طلعتی2؛ سید محمد علوی* 3 | ||
| 1دکتری تخصصی، دانشگاه علوم وفنون هوایی شهید ستاری، تهران، ایران | ||
| 2دانشجوی دکتری، دانشگاه علوم وفنون هوایی شهید ستاری، تهران، ایران | ||
| 3دانشیار،دانشگاه جامع امام حسین(ع)،تهران،ایران | ||
| تاریخ دریافت: 01 خرداد 1402، تاریخ بازنگری: 08 تیر 1402، تاریخ پذیرش: 13 مرداد 1402 | ||
| چکیده | ||
| افزایش تقاضا برای یکپارچه‌سازی مدارهای گسترده با هزینه پایین، عملکرد با توان مصرفی پایین در قالب یک تراشه یکی از مهمترین مسائل روز برای طراحان شده است. ازاینرو تلاشهای فراوانی برای ساخت مدارات و سیستمهای مجتمع شدة RF در محدوده فرکانسی گیگاهرتز و با استفاده از فنّاوری CMOS انجام‌گرفته است. اساساً استفاده از سنتزکننده‌های فرکانسی مبتنی بر حلقههای قفل فاز یکی از مهمترین بلوک‌های سازندة یک فانکشن ژنراتور است که وظیفة تولید سیگنال حامل را داشته و یکی از مهمترین و حساسترین بلوک‌های فانکشن ژنراتور است؛ چون در فرکانس‌های بالا کار می‌کند و سهم مصرف توان آن در فانکشن ژنراتور زیاد است. در این پژوهش یک طراحی و شبیهسازی سنتزکننده فرکانسی در نرم‌افزار Cadence RF-Spectre جهت استفاده در رادارهای باند X پیاده‌سازی شده است. نتایج این پژوهش نشان میدهد تکنیک خطی‌سازی جدید طراحی‌شده جریان‌های CP در مقایسه با جریان CP بدون تکنیک خطی‌سازی مطابقت بالایی دارد و حداکثر عدم تطابق حدود 0.4 میکروثانیه در ولتاژ کنترل بین 0.2 تا 1.6 ولت است. مصرف برق کسری -N طراحی شده حدود 6.579 میکرو وات با یک منبع تغذیه 1.8 ولتی است در سنتزکننده، نویز فاز VCO با فرکانس حامل 10 گیگاهرتز، در آفست 1 مگاهرتز برابر dBc/Hz 106- است و همچنین توان منابع باند جانبی به dBc55 - کوتاهتر از سیگنال حامل (در فرکانس 10.004 گیگاهرتز) رسیده است. | ||
| کلیدواژه‌ها | ||
| باند X؛ حلقه قفل فاز؛ نویز فاز؛ فیلتر حلقه؛ کسری-N | ||
| عنوان مقاله [English] | ||
| Presenting an Optimal Method of a Fractional-N Synthesizer to Reduce the Power Consumption of the Phase-Locked Loop with Delta-Sigma Modulator in x-Band Radars | ||
| نویسندگان [English] | ||
| Houman Akbarzade Khoshkeh Roud1؛ saeed Talati2؛ Seyed Mohammad Alavi3 | ||
| 1PhD, Shahid Sattari University of Aeronautical Sciences and Technology, Tehran, Iran | ||
| 2PhD student, Shahid Sattari University of Aeronautical Sciences and Arts, Tehran, Iran | ||
| 3Associate Professor, Imam Hossein University, Tehran, Iran | ||
| چکیده [English] | ||
| Increasing demand for the integration of wide circuits with low cost, and performance with low power consumption in the form of a chip has become one of the most important issues of the day for designers. Therefore, many efforts have been made to build RF integrated circuits and systems in the GHz frequency range using CMOS technology. The use of frequency synthesizers based on phase lock loops is one of the most important building blocks of a function generator, which has the task of producing the carrier signal and is one of the most important and sensitive function blocks of the generator; Because it works at high frequencies and the contribution of its power consumption in the generator function is high. This research has implemented a design and simulation of a frequency synthesizer for use in X-band radars. The results of this research show that in the synthesizer, the phase noise of the VCO with a carrier frequency of 10 GHz, at an offset of 1 MHz is equal to -106 dBc/Hz. The power of the sideband sources is 55 dBc - shorter than the carrier signal (at a frequency of 10.004 GHz) it arrives. | ||
| کلیدواژه‌ها [English] | ||
| X band, Phase locked loop, Phase noise, Loop filter, Fractional-N | ||
| مراجع | ||
|
1. L. Wu, T. Burger, P. Schönle and Q. Huang, "A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain," in IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1254-1264, April 2021, doi: 10.1109/JSSC.2020.3047431. 2. Y. Fu, L. Li and D. Wang, "A Fractional-N Divider for Phase-Locked Loop with Delta-Sigma Modulator and Phase-Lag Selector," 2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Melbourne, VIC, Australia, 2018, pp. 1-3, doi: 10.1109/RFIT.2018.8524055. 3. H. Liu et al., "A 265- μ W Fractional- N Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3478-3492, Dec. 2019, doi: 10.1109/JSSC.2019.2936967. 4. B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill Higher Education, 2000. 5. B. Miller and B. Conley “A multiple modulator fractional divider” in ,Proceedings of the 44th Annual Symposium on Frequency Control, pp. 559–568, 1990. 6. T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski “Delta-sigma modulation in fractional-N frequency synthesis” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, 1993. 7. Hosseini, Kaveh, and Michael Peter Kennedy “Minimizing Spurious Tones in Digital Delta-Sigma Modulators” Springer Science & Business Media, 2011. 8. E. Temporiti, et. al “A 700kHz Bandwidth Σ∆ Fractional Synthesizer With Spurs Compensation and Linearization Technique for WCDMA Applications” I EEE Jo urn a l o f S o l id - S ta te C i rc uits , vol. 39, pp. 1446–1454, Sept. 2004. 9. Yu, Xrger, P. Schönle and Q. Huang, "A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain," in IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1254-1264, April 2021, doi: 10.1109/JSSC.2020.3047431. 13. Y. Chen, J. Gong, R. B. Staszewski and M. Babaie, "A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple," in IEEE Journal of Solid-State Circuits, vol. 57, no. 6, pp. 1749-1764, June 2022. 14. W. Wu et al., "32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 444-446. 15. Q. Zhang, S. Su, C. -R. Ho and M. S. -W. Chen, "29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 410-412, doi: 10.1109/ISSCC42613.2021.9365819. 16. J. Qiu et al., "32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 454-456, doi: 10.1109/ISSCC42613.2021.9365861. 17. W. Wu et al., “A 28-nm 75-fsrms analog fractional-N sampling PLL with a highly linear DTC incorporating background DTC gain calibration and reference clock duty cycle correction,” IEEE J. Solid-State Circuits, vol. 54, no. 5, pp. 1254–1265, May 2019. 18. Y. He et al., “A 673 μW 1.8-to-2.5 GHz divider less fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 420–421. 19. V. K. Chillara et al., “An 860 μW 2.1-to-2.7 GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth smart and ZigBee) applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 172–173. 20. H. Liu, D. Tang, Z. Sun, W. Deng, H. C. Ngo, and K. Okada, “A sub-mW fractional-N ADPLL with FoM of −246 dB for IoT applications,” IEEE J. Solid-State Circuits, vol. 53, no. 12, pp. 3540–3552, Dec. 2018. 22. Talati, S., and M. R. Hasani Ahangar. “Radar data processing using a combination of principal component analysis methods and self-organizing and digitized neural networks of the learning vector.” Electronic and Cyber Defense Vol.(9).2 (2021): pp1-7. 23. Talati, S., & Hassani Ahangar. M. R. (2020) “Combining Principal Component Analysis Methods and Self-Organized and Vector Learning Neural Networks for Radar Data”, Majlesi Journal of Telecommunication Devices, 9(2), 65-69. 24. Hassani Ahangar, M. R., Talati, S., Rahmati, A., & Heidari, H. (2020). “The Use of Electronic Warfare and Information Signaling in Network-based Warfare”. Majlesi Journal of Telecommunication Devices, 9(2), 93-97. 25. Talati, S., Alavi, S. M., & Akbarzade, H. (2021). “Investigating the Ambiguity of Ghosts in Radar and Examining the Diagnosis and Ways to Deal with it”. Majlesi Journal of Mechatronic Systems, 10(2). 26. Etezadifar, P., & Talati, S. (2021). “Analysis and Investigation of Disturbance in Radar Systems Using New Techniques of Electronic Attack”. Majlesi Journal of Telecommunication Devices, 10(2), 55-59. 27. Talati, S., & Alavi, S. M. (2020). “Radar Systems Deception using Cross-eye Technique”. Majles Journal of Mechatronic Systems, 9(3), 19-21. 28. Talati, Saeed, et al. "Analysis and Evaluation of Increasing the Throughput of Processors by Eliminating the Lobe’s Disorder." Majlesi Journal of Telecommunication Devices 10.3, 2021, 119-123. 29. Talati, S., Abdollahi, R., Soltaninia, V., & Ayat, M. (2021). “A New Emitter Localization Technique Using Airborne Direction Finder Sensor. Majlesi Journal of Mechatronic Systems”, 10(4), 5-16. 30. Akbarzade, Houman, Seyed Mohammad Alavi, and Saeed Talati. "Investigating the Ambiguity of Ghosts in Radar and Examining the Diagnosis and Ways to Deal with it." Majlesi Journal of Mechatronic Systems 10.2 (2021): 17-20. 31. Talati, S., Etezadifar, P “Providing an Optimal Way to Increase the Security of Data Transfer using Watermarking in Digital Audio Signals” Majlesi Journal of Telecommunication Devices, 9(1), pp. 35-46, 2020. 32. Talati, S., Hassani Ahangar, M, “Analysis, Simulation and Optimization of LVQ Neural Network Algorithm and Comparison with SOM”, Majlesi Journal of Telecommunication Devices, 9(1), pp. 17-22, 2020. 33. S. Talati, A. Rahmati, and H. Heidari. (2019) “Investigating the Effect of Voltage Controlled Oscillator Delay on the Stability of Phase Lock Loops”, MJTD, vol. 8, no. 2, pp. 57-61. 34. Aslinezhad, M., Mahmoudi, O., & Talati, S. (2020). “Blind Detection of Channel Parameters Using Combination of the Gaussian Elimination and Interleaving”. Majlesi Journal of Mechatronic Systems, 9(4), 59-67. 35. Talati, S., & Amjadi, A. (2020). “Design and Simulation of a Novel Photonic Crystal Fiber with a Low Dispersion Coefficient in the Terahertz Band”. Majlesi Journal of Mechatronic Systems, 9(2), 23-28. 36. S. Talati, A. Rahmati, and H. Heidari, “Investigating the Effect of Voltage Controlled Oscillator Delay on the Stability of Phase Lock Loops”, MJTD, vol. 8, no. 2, pp. 57-61, May 2019. 37. Saeed. Talati, Behzad. Ebadi, Houman. Akbarzade “Determining of the fault location in distribution systems in presence of distributed generation resources using the original post phasors“. QUID 2017, pp. 1806-1812, Special Issue No.1- ISSN: 1692-343X, Medellin-Colombia. April 2017. 38. O. Sharifi-Tehrani and S. Talati, “PPU Adaptive LMS Algorithm, a Hardware-Efficient Approach; a Review on”, Majlesi Journal of Mechatronic Systems, vol. 6, no. 1, Jun. 2017 39. Hashemi SM, Barati S, Talati S, Noori H. “A genetic algorithm approach to optimal placement of switching and protective equipment on a distribution network.” J Eng Appl Sci 2016; 11: 1395-1400. 40. Talati, S., EtezadiFar, P., Hassani Ahangar, M. R., Molazade, M“Investigation of Steganography Methods in Audio Standard Coders: LPC, CELP, MELP” Majlesi Journal of Telecommunication Devices, 12(1), pp. 7-15, 2023, doi: 10.30486/mjtd.2022.695928 41. Talati, S., EtezadiFar, P., Hassani Ahangar, M. R., Molazade, M “Investigation of Steganography Methods in Audio Standard Coders: LPC, CELP, MELP” Majlesi Journal of Telecommunication Devices, 12(1), pp. 7-15, 2023, doi: 10.30486/mjtd.2022.695928. 42. Talati, Saeed, and Pouria EtezadiFar. "Electronic attack on radar systems using noise interference." Majlesi Journal of Mechatronic Systems 10.3, 2021, 7-11. 43. Seyed Morteza Ghazali, Jalil Mazloum, Yasser Baleghid. “Modified binary salp swarm algorithm in EEG signal classification for epilepsy seizure detection” Biomedical Signal Processing and Control. Volume 78, September 2022. 44. Talati, Saeed, Ghazali, Seyed Morteza, SoltaniNia, VahidReza, “Design and construct full invisible band metamaterial-based coating with layer-by-layer structure in the microwave range from 8 to 10 GHz” Journal of Physics D: Applied Physics. Volume 56, Number 17. 2023. DOI 10.1088/1361-6463/acb8c7. 45. Seyed M. Ghazali; Y. Baleghi. "Pedestrian Detection in Infrared Outdoor Images Based on Atmospheric Situation Estimation". Journal of AI and Data Mining, 7, 1, 2019, 1-16. 47. Mohammadi, H., Halili, K., Soltaninia, V., Bayat, M., Talati, S. (2023). 'Presenting a New Model of Optimal Coordinated beam former Vector Selection in DRFM for Radar Jamming', Majlesi Journal of Telecommunication Devices, 12(3), pp. 141-147. doi: 10.30486/mjtd.2023.1986716.1034 48. Soltaninia, V., Talati, S., Khatmi, S. M., Ghaffari, K. (2023). 'Presenting a New Steganography Method Based on Wavelet Transform in Gray Image', Majlesi Journal of Telecommunication Devices, 12(2), pp. 105-111. doi: 10.30486/mjtd.2023.1983555.1031 49. Talati, S., EtezadiFar, P., Hassani Ahangar, M. R., Molazade, M. (2023). 'Investigation of Steganography Methods in Audio Standard Coders: LPC, CELP, MELP', Majlesi Journal of Telecommunication Devices, 12(1), pp. 7-15. doi: 10.30486/mjtd.2022.695928. | ||
|
آمار تعداد مشاهده مقاله: 230 تعداد دریافت فایل اصل مقاله: 27 |
||
