بررسی روش‌های مقابله با حملات کانال جانبی از طریق منطق تفاضلی پویا

[1]      M. Tehranipoor and C. eds. Wang, “Introduction to hardware security and trust,” Springer Science & Business Media, 2011.##

[2]      P. Yu and P. Schaumont, “Secure FPGA circuits using controlled placement and routing,” in Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis (ACM), 2007.##

[3]      T. Popp and S. Mangard, “Masked dual-rail pre-charge logic: Dparesistance without routing constraints,” in International Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2005.##

[4]      A. Wild, A. Moradi, and T. Guneysu, “Glifred: Glitch-free duplicationtowards power-equalized circuits on FPGAs,” IEEE Transactions on Computers, no. 1, pp. 1–1, 2017.##

[5]      Z. Chen and Y. Zhou, “Dual-rail random switching logic: a countermeasure to reduce side channel leakage,” in International Workshop on Cryptographic Hardware and Embedded Systems, 2006.##

[6]      M. Bucci, L. Giancane, R. Luzzi, and A. Trifiletti, “Three-phase dualrail pre-charge logic,” in International Workshop on Cryptographic Hardware and Embedded Systems, pp. 232–241, 2006.##

[7]      W. He, E. de la Torre, and T. Riesgo, “An interleaved      epe-immune PA-DPL structure for resisting concentrated em side channel attacks on FPGA implementation,” in International Workshop on Constructive SideChannel Analysis and Secure Design, 2012.##

[8]      S. Guilley, S. Chaudhuri, L. Sauvage, T. Graba, J.-L. Danger, P. Hoogvorst, V.-N. Vong, and M. Nassar, “Place-and-route impact on the security of DPL designs in FPGAs,” in Proceedings of IEEE International Workshop on Hardware-Oriented Security and Trust (HOST), 2008.##

[9]      R. Soares, N. Calazans, V. Lomne, P. Maurine, L. Torres, and M. Robert, “Evaluating the robustness of secure triple track logic through prototyping,” in Proceedings of the 21^st annual symposium on Integrated circuits and system design (ACM), 2008.##

[10]      T. Popp, M. Kirschbaum, T. Zefferer, and S. Mangard, “Evaluation of the masked logic style mdpl on a prototype chip,” in International Workshop on Cryptographic Hardware and Embedded Systems, 2007.##

[11]      M. Masoumi, A. Dehghan Menshadi, E. Madadi, S. Saee Moghadam, “A New and Efficient Method of Mass Masking and its Resistance Assessment to Power Analysis,” Journal of Electronical & Cyber Defence, vol. 6, no. 2, 2018.##

 [12]      K. Tiri, M. Akmal, and I. Verbauwhede, “A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards,” in Proceedings of the 28^th IEEE European Conference on Solid-State Circuits (ESSCIRC), 2002##.

[13]      K. Tiri and I. Verbauwhede, “A logic level design methodology for a secure DPA resistant asic or FPGA implementation,” in Proceedings of IEEE Europe Conference and Exhibition on Design, Automation and Test, vol. 1, pp. 246–251, 2004.##

[14]      A. Moradi and A. Poschmann, “Lightweight Cryptography and DPA Countermeasures: A Survey,” Financial Cryptography and Data Security Lecture Notes in Computer Science, pp. 68–79, 2010.##

[15]      W. He, A. Otero, E. de la Torre, and T. Riesgo, “Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic,” Microprocessors and Microsystems, vol. 38, no. 8, pp. 899–910, 2014.##

[16]      R. Velegalati and J.-P. Kaps, “Improving security of SDDL designs through interleaved placement on Xilinx FPGAs,” in Proceedings of IEEE International Conference on Field Programmable Logic and Applications (FPL), 2011.##

[17]      A. Razafindraibe, M. Robert, and P. Maurine, “Improvement of dual rail logic as a countermeasure against DPA,” in Proceedings of IEEE IFIP International Conference on Very Large Scale Integration (VLSI-SoC), 2007.##

[18]      M. Nassar, S. Bhasin, J.-L. Danger, G. Duc, and S. Guilley, “BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation,” in Proceedings of the Conference on Design, Automation and Test in Europe, 2010.##

[19]      A. Moradi and V. Immler, “Early propagation and imbalanced routing, how to diminish in FPGAs,” in International Workshop on Cryptographic Hardware and Embedded Systems, 2014.##

[20]      D. Jayasinghe, A. Ignjatovic, J. A. Ambrose, R. Ragel, and S. Parameswaran, “Quadseal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks,” in Proceedings of IEEE International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2015.##

[21]      A. Wild, A. Moradi, and T. Guneysu, “Evaluating the duplication of dual-rail precharge logics on FPGAs,” in International Workshop on Constructive Side-Channel Analysis and Secure Design, 2015.##